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Bui, H. T., & Savaria, Y. (2008). Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-Ghz Frequency-Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(3), 766-774. Lien externe
Bui, H. T., & Savaria, Y. (avril 2006). High speed differential pulse-width control loop based on frequency-to-voltage converters [Communication écrite]. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006), Philadelphia, USA. Lien externe
Bui, H. T., & Savaria, Y. (juillet 2005). Design and analysis of XOR gates for high-speed and low-jitter applications [Communication écrite]. 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2005), Orlando, Floride. Non disponible
Bui, H. T., & Savaria, Y. (juillet 2005). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
Bui, H. T., & Savaria, Y. (juin 2005). High-speed differential frequency-to-voltage converter [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005). Lien externe
Bui, H. T., & Savaria, Y. (juillet 2004). 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 mu m CMOS [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Bui, H. T., & Savaria, Y. (mai 2004). Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. Lien externe
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (mai 2010). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS) [Communication écrite]. IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France. Lien externe
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (juin 2009). Design and optimization of a low complexity all-digital digital-to-analog converter [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (juin 2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (août 2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). Lien externe
Vezant, B., Mansuy, C., Bui, H. T., & Boyer, F.-R. (juin 2009). Direct digital synthesis-based all-digital phase-locked loop [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
