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Documents dont l'auteur est "Blaquière, Y."

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Nombre de documents: 8

B

Berrima, S., Blaquière, Y., & Savaria, Y. (mai 2017). A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (4 pages). Lien externe

C

Cantin, M.-A., Blaquière, Y., Savaria, Y., Lavoie, P., & Granger, É. (mai 2000). Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. Lien externe

G

Guillemot, M., Blaquière, Y., & Savaria, Y. (mai 2013). Software Rendering Methods to Display Wafer Scale Integrated Circuit Dataset [Communication écrite]. 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2013), Regina, Sask, CAN. Lien externe

Granger, É., Blaquière, Y., Savaria, Y., Cantin, M.-A., & Lavoie, P. (août 1996). VLSI architecture for fast clustering with fuzzy ART neural networks [Communication écrite]. 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP 1996), Venice, Italy. Lien externe

H

Hussain, W., Savaria, Y., & Blaquière, Y. (mai 2013). An interface for the I2C protocol in the WaferBoard TM [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, Chine. Lien externe

L

Lepercq, E., Valorege, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquière, Y., & Savaria, Y. (octobre 2009). An interconnection network for a novel reconfigurable circuit board [Communication écrite]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. Lien externe

P

Poiré, P., Cantin, M.-A., Daniel, H., Blaquière, Y., Savaria, Y., Pocek, K. L., & Arnold, J. M. (avril 1998). A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing [Communication écrite]. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA. Lien externe

Poiré, P., Savaria, Y., Daniel, H., Cantin, M. A., & Blaquière, Y. (novembre 1998). Hardware/software codesign of a Fuzzy ART neural clusterer : The benefits of configurable computing [Communication écrite]. 3rd Conference on Configurable Computing, Boston MA, USA. Lien externe

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