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Bergeron, E., Feeley, M., & David, J. P. (mars 2008). Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs [Communication écrite]. 17th International Conference on Compiler Construction (CC 2008), Budapest, Hungary. Lien externe
Bergeron, E., Feeley, M., Daigneault, M.-A., & David, J. P. (juin 2008). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. Lien externe
Bergeron, E., Feeley, M., & David, J. P. (août 2007). Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. Lien externe
Bergeron, E., Saint-Mleux, X., Feeley, M., & David, J. P. (juin 2005). High level synthesis for data-driven applications [Communication écrite]. 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), Montréal, Québec. Lien externe
David, J. P., & Bergeron, E. (septembre 2004). An intermediate level HDL for system level design [Communication écrite]. 7th Forum on Specification and Design Languages (FDL 2004), Lille, France. Non disponible
David, J. P., & Bergeron, E. (juillet 2004). A step towards intelligent translation from high-level design to RTL [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2004), Banff, Canada. Lien externe
