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Bouchebaba, Y., Gagne, V., Nicolescu, G., & Aboulhamid, M. (2006, June). SoC memory optimization using loop transformations [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Cyr, G., Bois, G., & Aboulhamid, M. (2004). Generation of processor interface for SoC using standard communication protocol. IEE Proceedings. Computers and Digital Techniques, 151(5), 367-376. External link
Charest, L., Aboulhamid, M., & Bois, G. (2003). Applying multi-paradigm and patterns approaches to hardware/software design and reuse. In Patterns and skeletons for parallel and distributed computing (97-325). External link
Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Determining schedules for reducing power consuption using mulyiple supply voltages [Paper]. International Conference on Computer Design (ICCD 2001), Austin, Texas. External link
Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Efficient methods for reducing register and phase requirements for synchronous circuits derived using software pipeling techniques [Paper]. European Conference on Circuit Theory and Design, Espoo, Finland. Unavailable
Moss, L., De Nanclas, M., Filion, L., Fontaine, S., Bois, G., & Aboulhamid, M. (2007, April). Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France. External link
Quinn, D., Lavigueur, B., Bois, G., & Aboulhamid, M. (2004, February). A system level exploration platform and methodology for network applications based on configurable processors [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. External link
Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (2002, July). Aspect Partitioning for Hardware Verification Reuse [Paper]. System-on-Chip for Real-Time Applications. External link
