Items where Author is "Vialletelle, Philippe"
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A word cloud is a visual representation of the most frequently used words in a text or a set of texts. The words appear in different sizes, with the size of each word being proportional to its frequency of occurrence in the text. The more frequently a word is used, the larger it appears in the word cloud. This technique allows for a quick visualization of the most important themes and concepts in a text.
In the context of this page, the word cloud was generated from the publications of the author {}. The words in this cloud come from the titles, abstracts, and keywords of the author's articles and research papers. By analyzing this word cloud, you can get an overview of the most recurring and significant topics and research areas in the author's work.
The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
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Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part I: Modelling. International Journal of Production Research, 50(23), 6835-6851. External link
Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part II: Evaluation. International Journal of Production Research, 50(23), 6852-6869. External link
Shanoun, M. , Vialletelle, P., & Bassetto, S. (2010, November). A dynamic sampling algorithm [Paper]. 13th ARCSIS Technical & Scientific Meeting, Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable
Sahnoun, M. , Vialletelle, P., Bassetto, S., Tollenaere, M., & Bastoini, S. (2010, November). Historical wafer-at-risk construction in STMicroelectronics 300mm wafer fab in crollesoptimizing return on inspection through defectivity smart skipping [Paper]. Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable
Sahnoun, M., Vialletelle, P., Bastoini, S., Bassetto, S., & Tollenaere, M. (2010, October). Optimized return on inspection through smart-sampling [Paper]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo, Japan. External link
Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (2010, October). Optimized design of control plans based on risk exposure and resources capabilities [Paper]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo. Japan. External link
Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (2010, November). Operational risk evaluation and control plan design [Paper]. 13th ARCSIS Technical & Scientific Meeting, Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable